One of the most important steps in the design of integrated circuit chips is the layout or routine of conductor paths to be placed on a chip. Modern integrated circuit technology involves thousands of conductor paths that must be routed from one connection point to another to interconnect various logic units. The conductor paths are provided as bus cells placed in various locations on a chip and occupying a significant portion of a chip.
The size of a chip is an important factor in the ultimate cost of the integrated circuit. The more the chip size is reduced, the more chips that can be produced per wafer. The larger the number of integrated circuits which are manufactured per wafer, the smaller are the production costs per chip. Reducing the area occupied by bus cells reduces total chip size and, hence, unit chip cost.
A plurality of parallel bus channels are provided in a bus cell area to carry the signals to be transferred through the bus cell. Each bus channel occupies a strip having sufficient width to carry one signal passing through the bus cell. While to minimize the occupied chip area, the width of each channel and the spaces between the channels should be reduced, at least minimum channel widths and spaces must be maintained to avoid short circuits and parasitic effects despite slight variations in the manufacturing process due to the presence of minute submicron particulates that are invariably present in the semiconductor processing facility.
In view of the above, it would be desirable to minimize the number of bus channels in each bus cell to reduce the chip area occupied by the bus cell.
Further, as the layout of conductor paths is performed by a computerized routine system, it would be desirable to use a systematic and iterative process to reduce the bus cell size.